PD CAD Engineer (SI50FT RM 3837)

Position: PD CAD Engineer (SI50FT RM 3837)

Job Overview
We are seeking a PD CAD Engineer with 5+ years of experience in physical design and CAD flow development, with strong hands-on expertise in Synopsys Fusion Compiler–based physical implementation flows. The role involves building, customizing, and supporting robust RTL-toGDSII methodologies, closely collaborating with design to enable predictable PPA closure on advanced technology nodes.
This role requires solid execution capability, deep tool knowledge, and a strong understanding of PnR and signoff methodologies, not just tool operation.

Key Responsibilities

• Develop, customize, and maintain end-to-end RTL-to-GDSII physical design CAD flows, with primary focus on Synopsys Fusion Compiler.
• Drive automation and methodology improvements across floor-planning, placement, CTS, routing, and post-route optimization stages.
• Effectively utilize Fusion Compiler unified flow for implementation, optimization, and convergence of PPA metrics.
• Support physical designers in timing, power, and area closure, including debug of complex convergence issues.
• Build and maintain TCL-based automation frameworks; use Perl/Python where appropriate for flow orchestration and reporting.
• Integrate MCMM methodologies into PD flows and ensure correctness and scalability across projects.
• Collaborate with signoff teams to align implementation and signoff requirements, minimizing late-stage surprises.
• Perform tool feature evaluation, regression testing, and benchmarking for new Fusion Compiler releases.
• Provide clear documentation, flow guidelines, and technical support to design teams.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or a related field.
• 5+ years of industry experience in physical design or PD CAD methodology development.
• Strong hands-on experience in place-and-route and CAD flow enablement for complex
  SoCs or blocks.

Must-Have Skills
Fusion Compiler Expertise

• Strong hands-on experience with Synopsys Fusion Compiler in production tape-out flows.
• In-depth understanding of Fusion Compiler architecture, unified implementation flow, and optimization engines.
• Experience configuring and tuning Fusion Compiler for placement, CTS, routing, and postroute optimization.
• Ability to debug and resolve congestion, timing, power, and DRC-related issues within Fusion Compiler.

PnR Flow & Methodology

• Solid understanding of end-to-end physical design flow:
• Strong grasp of PnR best practices and methodology trade-offs affecting PPA and convergence.
• Experience handling MCMM constraints, scenarios, and optimization strategies.

Signoff Flow & Methodology

• Clear understanding of timing signoff methodology, including setup/hold closure and ECO
  strategies.
• Familiarity with physical verification signoff: DRC, LVS, and integration with signoff tools.
• Ability to align implementation flows with signoff requirements to reduce iteration cycles and risk.

Automation & Scripting

• Strong proficiency in TCL scripting for PD flow automation and customization.
• Working knowledge of Perl and/or Python for automation, data analysis, and reporting.

Preferred Skills

• Experience with advanced technology nodes (sub-10nm) and related PD challenges.
• Knowledge of low-power design techniques and their impact on physical implementation.
• Prior experience supporting multiple design teams through reusable, scalable CAD flows.

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