DV Engineer – RISC-V CPU / Cache (SI50FT RM 3964)

Position: DV Engineer – RISC-V CPU / Cache (SI50FT RM 3964)

Role Summary:
We are looking for a Senior Design Verification Engineer with deep hands-on experience in RISC-V CPU cores and cache subsystems. The role involves pre-silicon verification of processor micro-architecture and memory hierarchy.

Mandatory Skills

• 5+ years of hands-on RISC-V DV experience
• Strong experience verifying RISC-V CPU cores (in-order or out-of-order)
• Solid understanding of RISC-V ISA and privilege architecture
• Experience verifying L1/L2 cache, cache coherency, and memory ordering
• Expertise in SystemVerilog, UVM
• Strong debugging skills at RTL and micro-architecture level

Responsibilities

• Develop and maintain UVM-based verification environments
• Create directed and constrained-random tests for CPU and cache
• Verify pipeline, exceptions, interrupts, MMU, and cache behavior
• Debug functional issues and work closely with design and architecture teams

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