SOC RTL Design Engineer (BB68FT RM 4110)

Position: SOC RTL (BB68FT RM 4110)

Job Description:
We are looking for profiles with 6-8 years’ experience in SoC RTL/DFx verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Test mode. It’s good to have pattern generation and Silicon debug experience.

*******************************************************************************************************************************************