Research & Development – RF, Analog and Mixed Signal – Design Engineer – Analog – III (RM 4539)

Domain – Analog FE. Experience – More than 12 years.

Scope of Responsibilities:
AsiaPac “Design Enablement Engineering Support” team is focused on the implementation of methodology in close collaboration with the AsiaPac design teams and on the tactical support of all SoC design development.

The candidate will contribute, within an international team, to the deployment and support, flows and tools of design of integrated circuits used in the company. He / She will also be the main interlocutor of design teams to pro-actively understand their needs, to implement solutions that address the resolution of new technical challenges or recurring problems impacting the development of integrated circuits.

The mission consists in particular of:
– Project Liaison dedicated to a specific Business design team. In this role, he / she will make sure to coordinate, implement solutions that meet the needs of design teams in a proactive way in collaboration with the global team DE Engineering Support, DE design flow and technology development teams and IT teams.
– Support design teams on flow-integrated design tools: diagnosis and problem solving; development and customization of design tools in collaboration with DE design flow and technology development teams; deployment of new tools according to the needs of the design teams; training of design teams in the evolution of the design flow.
– He / She will also be the privileged interface of the design team for the implementation of the needs and the resolution of the problems having a dependence with the IT organization.
– He / she should be able to provide CAD expertise related to a defined area of CAD technical competence (see technical skills listed below).

By this area of technical competence, he/she will be engaged to have cooperation with Design Teams at AsiaPac or World level as an expert to resolve challenges faced by BU design teams. He/She will also be involved in the implementation of new methods by participating in the development of new tools with our integrated circuit development software vendor partners or with the DE design flow and technology development teams.

Required Skills:
Excellent knowledge parametric and functional verification: Functional Verification and test regression (Incisiv, vManager, vPlanner); Parametric Verification and test regression (Cadence Virtuoso ADE-XL based); Skilled in Simulators (Spectre, AFS, Incisive, VCS-AMS); AMS model development (Wreal, SystemVerilog, VerilogAMS, UVM, UNL); Testbench technologies (UVM); Fastspice simulator (Cadence Spectre or Synopsys CustomSim – FineSimPro); Good IT skills and global understanding on IT – CAD optimization.
Good Knowledge TCL / Shell / PERL / Cadence SKILL / Python Scripting.
Good IT infra and LSF skills.