STA CAD Engineer (SI RM 2792)

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Position : STA CAD Engineer (SI RM 2792)

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Job Overview:
The STA CAD Engineer will develop, maintain, and optimize static timing analysis (STA) flows and methodologies, with a primary focus on Synopsys PrimeTime. This role requires strong expertise in STA, CAD flow development, and proficiency with TCL, Perl, and Python scripting for automation. Familiarity with 3D IC signoff is a plus.

Key Responsibilities:

• Develop, support, and optimize STA CAD flows and methodologies using Synopsys PrimeTime for VLSI designs.
• Collaborate with design and implementation teams to establish timing constraints and ensure timing closure.
• Develop scripts and automation solutions using TCL, Perl, and Python for timing analysis, report generation, and optimization.
• Work closely with physical design and verification teams to ensure timing requirements are met across multiple process, voltage, and temperature (PVT) corners.
• Generate detailed timing reports, identify and resolve timing violations, and implement optimizations.
• Evaluate and implement new EDA tools and methodologies to improve STA efficiency and accuracy.

Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, VLSI, or a related field.
• Minimum of 5+ years of relevant experience in static timing analysis, CAD flow development, and Synopsys PrimeTime.
• Proficiency in TCL, Perl, and Python scripting is necessary for CAD automation and customization.
• Familiarity with advanced technology nodes (e.g., 7nm, 5nm) and timing constraints in complex designs.
• Strong understanding of timing closure methodologies and STA best practices.

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