Position: Mixed-Signal Verification Engineer (BB60FT RM 4426) Key skills: Mixed-Signal Co-Simulation, SystemVerilog, UVM, Verilog-AMS/RNM, Cadence Xcelium, Virtuoso, Spectre, Behavioral Modeling, Python/Perl/TCL, Model vs Schematic Verification **********************************************************************************************

Position: ASIC Engineer 4 (BB60FT RM 4424) Key Skills: SoC/IP Verification, SystemVerilog, UVM, PCIe, DDR, Test Controller, MBIST, DFT Architecture, AI Tools & Methodologies, Python/Perl/TCL. **********************************************************************************************

Position: Validation Engineer – II (BB60FT RM 4414) Key Skills: System-level Validation & Verification, NFC, Test Automation, C/C++/Java/Python, Wireless Technologies (NFC, Bluetooth, Wi-Fi, Zigbee), Oscilloscope, Logic Analyzer, RF Debugging, ISO7816/ISO14443. ***********************************************************************************************

Position: STA Verification Engineer (BB60FT RM 4355) Mandatory Education: BE or MTech (mandatory) Key responsibilities **************************************************************************************************************

Position: Observability & FinOps (TT60ST RM 4347) Interview process – Virtual interviewInterviews are on Friday 2nd and Saturday 3rd Oct. Must have skills: ****************************************************************************************************

Position: RUCA (TT60ST RM 4346) Interview process – Virtual interviewInterviews are on Friday 2nd and Saturday 3rd Oct. We are looking for a Java/Python developer to enhance a custom reusable-asset management application. The application follows concepts similar to IBM DNG/ELM, including asset/artifact management, metadata, tagging, workflows and traceability. The current focus is to automate data …