Design Verification Low Power (CE510SI RM 4586)

Position: Design Verification Low Power (CE510SI RM 4586)

Shift timing : 9-6
Work mode : Work from office
Education Required : BE or ME Electronics

Experience Level:

• 1 Lead HC with 8 to 10 years
• 5 Engineers HC with 5-8 years

Relevant Experience required:

• 1 Lead HC with 8 to 10 years
• 5 Engineers HC with 5-8 years

Must have Skills:

• Own verification of next-generation derivatives of existing subsystems (Die2Die, Compute SS, Audio, DSS, Neural SS, Security) by reusing and porting existing UVM environments for unchanged functionality while developing verification content for new features and design deltas.
• Drive low-power verification, including UPF-based power-aware simulations, retention/isolation validation, power sequencing, clock/power gating, wake-up flows, and coverage closure for power reduction features.
• Perform Formal Verification at block and SoC level, including FPV, formal connectivity verification, UNR analysis, coverage closure/merge, and formal low-power verification for retention and isolation scenarios using JasperGold apps.
• Collaborate closely with DV Lead,  Architecture, Design, Power, and FW teams to drive execution, debug, signoff readiness, and timely closure of verification milestones.
• Strong expertise in SystemVerilog/UVM, regression management, coverage closure, and subsystem/SoC-level debug.
• Deep experience in Low-Power Verification using UPF, power-aware simulation, retention/isolation checks, clock/power gating validation, wake-up flows, and low-power architecture concepts.
• Hands-on expertise with JasperGold/VC Formal for FPV, Formal Connectivity, UNR analysis, Assertion-Based Verification (SVA), Coverage Merge/Closure, and low-power formal verification.
• Experience reusing and extending existing verification environments for derivative designs, validating design deltas, and driving efficient verification signoff.
• Strong technical leadership, problem-solving, and cross-functional collaboration skills with the ability to independently drive verification closure

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