DFT Engineer (ST49FT RM 4569)

Position: DFT Engineer (ST49FT RM 4569)

Qualification: B.E./B.Tech./M.E./M.Tech. in ECE, EEE, or a related engineering discipline.

Key Responsibilities & Skills:

• Strong expertise in SpyGlass DFT, Scan Architecture (SSN Topology), ATPG, and fault models.
• Hands-on experience in JTAG, Memory BIST, BIRA/BISR, and DFT implementation.
• Experience in DFT verification, Gate-Level Simulation (GLS), timing analysis, DRC debugging, and ATPG coverage improvement.
• Proficiency in RTL coding and shell scripting.
• Experience with ATE, post-silicon validation, and manufacturing debug.
• Knowledge of X86 CPU architecture, advanced process nodes, and hierarchical DFT is preferred.
• Senior candidates should have strong technical leadership and cross-functional collaboration skills.

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