DMS Verification Engineer (BB50FT RM 4386)

Position: DMS Verification Engineer (BB50FT RM 4386)

Role Overview
We are seeking a DMS Verification Engineer with 5+ years of experience in analog/mixed-signal behavioral modeling and full-chip verification using SV-RNM, custom UDNs, and UVM.

Key Responsibilities

• Develop behavioral models and perform AMS/DMS verification at block, subsystem, and chip-top levels.
• Create verification plans, UVM environments, and self-checking testcases.
• Verify mixed-signal products involving PLLs, ADCs, DACs, power-management circuits, SerDes, bandgaps, oscillators, and clocking blocks.
• Perform analog-model, RTL, and gate-level SDF simulations.
• Debug simulations using Cadence Virtuoso, SimVision, Xcelium/DMSO, and Synopsys VCS.
• Manage regressions, coverage, verification metrics, and signoff using Cadence vManager.
• Drive functional/code coverage and analog verification closure.
• Collaborate with analog, digital, system, and verification teams.

Required Qualifications

• B.Tech/M.Tech in Electronics, Electrical, VLSI, or a related field.
• 5+ years of relevant AMS/DMS verification experience.
• Strong knowledge of analog and mixed-signal design concepts.
• Hands-on experience with SV-RNM, custom UDNs, UVM, and self-checking tests.
• Experience with functional/code coverage, regression management, and verification closure.
• Strong debugging, problem-solving, communication, and collaboration skills.
• Self-motivated and willing to learn new technologies.

Preferred Skills

• Cadence Virtuoso, SimVision, Xcelium/DMSO, Synopsys VCS, and vManager.
• Formal verification and metric-driven verification.
• Experience with complex semiconductor products and full-chip verification.

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