PAGLS/PARTL Verification Engineer (BB69ST RM 4445)

September 23, 2026
sradmin

Position: PAGLS/PARTL (BB69ST RM 4445)

Job Responsibilities

  • Responsible for building GLS environment (Unit delay & Timing) setup
  • Responsible for bring up Sanity simulations across cores with Unit delay & Timing sims
  • Work with Architecture, Design team to understand the low power design features and create verification plan
  • Develop verification components, testbench for low power verification and integrate third party VIPs/UVCs as required
  • Create constraint random verification environment using System Verilog, UVM
  • Perform Power Aware Verification in a random verification environment on the design
  • Regress and close the required Low Power coverage metrics to ensure high quality design

Minimum Skills

  • 8+ years of Design Verification experience.
  • Bachelor’s degree in Science, Engineering or closely related field.
  • 3+ years of hands-on experience in System Verilog, OVM/UVM based constrained random verification.
  • 3+ years of hands-on experience in developing GLS environment, GATE ID creation, verification components/UVCs, testbench for GLS verification
  • 3+ years of hands on testbench bring up, integrating third party VIPs, digital design, verification, debugging, and waveform debug
  • 2+ years of experience in UPF based Power Aware verification
  • 2+ years of experience in Functional coverage model development and/or code coverage closure
  • Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
  • Strong communication skills to interact with a global team.

Desirable

  • BE/ME degree in Electrical Engineering or equivalent.
  • Experience with Synopsys NLP (native Low Power) tool.
  • Working knowledge of GLS, PAGLS and scripting languages such as Perl, Python is a plus.
  • Worked on Low Power coverage metrics collection and coverage closure
  • Post-Silicon debug experience.
  • Knowledge of GPU/CPU/DDR/Bus preferred.
  • Formal verification experience (AND/OR) Low Power Formal Verification experience

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Job Category: PAGLS/PARTL
Job Type: Full Time
Job Location: Bangalore
Experience: 6-9 years
Notice period: 0-30 days

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