RTL – IP Integration Engineer (BB815FT RM 4140)

Position: RTL – IP Integration Engineer (BB815FT RM 4140)

Role Summary
We are looking for an experienced ASIC RTL engineer to join as a contractor on an IP integration project in the high-speed networking domain. The primary focus is integrating third part IPs, including interface bridging, protocol adaptation, and driving CDC/RDC signoff. You will work closely with Physical Design and Design Verification teams and are expected to contribute independently from day one.

Responsibilities

• Core Integration Work
  o Develop RTL glue logic, wrapper modules, and interface bridges required for third-party IP integration.
  o Integrate third party IPs covering protocol adaptation, interface timing, and tie-off management.
  o Own and drive CDC, RDC, and lint signoff for integrated IP blocks using Spyglass.
  o Define integration architecture: clock/reset topology, power domain boundaries, and interface specifications.
• RTL Design & Closure
  o Perform targeted RTL refactoring to resolve timing and area issues — including structural and algorithmic changes.
  o Conduct design reviews and provide constructive feedback on integration RTL submitted by other team members.
  o Support synthesis runs and interpret reports to guide RTL improvements during PD handoff.
• Collaboration & Documentation
  o Partner with the DV team to define integration testplans and support simulation-based and formal verification of integrated blocks.
  o Collaborate with the Physical Design team to ensure smooth RTL-to-GDS handoff, including constraint reviews.
  o Maintain integration documentation: IP interface specs, clock/reset architecture diagrams, and tie-off sheets.

Qualifications
Must Have

• Bachelor’s degree or higher in Electronics, ECE, or EE
• 8–15 years of ASIC RTL design experience.
• Hands-on experience integrating MAC IP with PCS and SerDes PHY, specifically at 100G or higher speeds.
• Strong understanding of multi-clock, multi-reset, and power domain design challenges, with a track record of CDC/RDC closure.
• Proven ability to refactor RTL to address timing and area challenges, including structural and algorithmic changes.
• Familiarity with synthesis flows and the ability to interpret and act on timing/area reports.

Nice to Have

• Background in networking or switching ASIC design.
• Exposure to 400G / 800G Ethernet standards and roadmaps.
• Knowledge of formal verification methods applied to integration blocks.

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