Senior Verification Engineer, DDR PHY (IRT60ST RM 4494)

Position: Senior Verification Engineer, DDR PHY (IRT60ST RM 4494)

Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY.

Must-have:

• DDR PHY architecture, DFI protocol, JEDEC standards (latest gens)
• LPDDR5/LPDDR4 hands-on experience
• Verilog/SystemVerilog, UVM/OVM
• Strong debug and root-cause skills, including SS/SoC/post-silicon issues

Good to have:

• Perl scripting
• Post-silicon bring-up, HW-SW debug
• AHB/AXI protocol knowledge

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