STA Engineer (BB58FT RM 3845)

Position: STA Engineer (BB58FT RM 3845)

First round of discussion will be F2F with their client. All 5 days WFO.

Job Description:
STA Engineer with expertise in full-chip timing closure. Should have hands-on experience performing end-to-end STA for large and complex designs and must be capable of independently driving timing closure activities.

Key Responsibilities:

• Perform full-chip STA using Cadence Tempus.
• Execute end-to-end timing analysis, including constraint validation, path analysis, debug, and timing closure.
• Analyse, interpret, and resolve timing violations across setup, hold, transition, and clock-related paths.
• Work closely with physical design, RTL, and synthesis teams to drive closure.
• Support sign-off activities for designs up to 8 million instances.
• Provide guidance on ECOs, constraints tightening, and optimization strategies.
• Deliver high-quality timing reports, sign-off summaries, and closure documentation.

Required Qualifications:

• 5+ years of STA experience in ASIC design flows.
• Strong working knowledge of Cadence Tempus (must-have).
• Proven ability in full-chip timing closure for medium to large designs.
• Capable of understanding timing paths deeply and independently closing timing issues.
• Experience handling designs up to 8M instances.
• Ability to collaborate effectively with cross-functional ASIC teams.
• Strong analytical and problem-solving abilities.

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