Position: Java fullstack (TV60ST RM 4434) Mandatory skills: Java MSB , React\Angular, Vulnerability RemediationDomain: Banking domain Role SummaryWe are looking for a Senior Java Full Stack Engineer with strong experience in Java/MSB, React or Angular, and application vulnerability remediation. The candidate should have hands-on coding experience and be capable of analyzing and fixing security vulnerabilities …

Position: Java MSB + Bigdata (TV60ST RM 4433) Mandatory skills: Java MSB, any bigdata tool like Scala, Apache Spark, SQOOP, Vulnerability RemediationDomain: Banking domain Role SummaryWe are looking for a senior Java professional with 6+ years of experience in Java development, Big Data technologies, and application vulnerability remediation. The candidate should have strong hands-on coding …

Position: Java MSB (Microservices, Springboot) (TV60ST RM 4432) Mandatory skills: Java MSB, SQL, AWS + Vulnerability remediationDomain: Banking domain Role SummarySenior engineer to handle the more complex, code-intensive remediation flagged by SVA (static), DVA (dynamic), SCA, and container scans across the Java portfolio. Key Responsibilities Mandatory Skills ************************************************************************************************************************

Position: Technical Lead- BSP, Hypervisior, Kernal, Boot Loader (TK712FT RM 4430) MANDATORY SKILLS : Automotive, Defect Ananlysis, Bug Fixing, BSP, Kernal, HyperV, Boot Loader Role OverviewThis role is for an Automotive BSP Engineer with strong hands-on experience in BSP, Kernel, Hypervisor, and Bootloader development. The candidate should be able to work on low-level platform software, …

Position: Mixed-Signal Verification Engineer (BB60FT RM 4426) Key skills: Mixed-Signal Co-Simulation, SystemVerilog, UVM, Verilog-AMS/RNM, Cadence Xcelium, Virtuoso, Spectre, Behavioral Modeling, Python/Perl/TCL, Model vs Schematic Verification **********************************************************************************************

Position: ASIC Engineer 2 (BB46FT RM 4425) Key Skills: ATPG Pattern Generation & Validation, Scan Insertion, DFT RTL/Gate-Level Implementation, Siemens/Synopsys/Cadence Tools, Verilog, VHDL, C/C++, TCL, Perl, Python. ********************************************************************************************************

Position: ASIC Engineer 4 (BB60FT RM 4424) Key Skills: SoC/IP Verification, SystemVerilog, UVM, PCIe, DDR, Test Controller, MBIST, DFT Architecture, AI Tools & Methodologies, Python/Perl/TCL. **********************************************************************************************

Position: Analog and Mixed Signal – Design Engineer – Analog – II (BB36FT RM 4423) Job Description: **********************************************************************************************

Position: Senior IP/SOC Design Engineer (BB810FT RM 4422) Responsibilities Job Description: Collaborate with cross-functional teams to ensure high-quality design implementation and successful product delivery. Required Skills and Qualifications *******************************************************************************************************

Position: Design Engineer – Verification (BB812FT RM 4421) Job SummaryThe Verification role will involve many aspects of Functional, Performance verification using most effective methodologies in context of Module/Subsystem/SoC /System Level. A strong ability to map requirements into a traceable verification plan is important. The ideal candidate will partner with local and global SoC and IP …