Position: Virtio/vSkipGen Engineer (CE79SI RM 3519) We are seeking an engineer to join our vSkipGen and Virtio development efforts. The ideal candidate will bring a mix of the following skills and attributes (not all are required, but a stronger match will enable faster contribution) Virtio expertise – Experience developing or extending Virtio devices (virtio-audio, virtio-gpu, …

Position: AX Functional (IA80FT RM 3424) JD for AX Functional consultant role. We are looking for people ready to work in 2012 version. Should have worked on implementation. Job Description: What You’ll Be Doing:ERP Analyst provides project coordination, functional expertise, and contributes to improvements and enhancements for mission-critical, enterprise-wide information systems. The ERP Analyst is …

Position: SOC Verification engineers (SI80FT RM 3512) Job Description: *******************************************************************************************************************************************

Position: Test Architect Technical Lead 2 (CE120SF RM 3511) Education Required: Bachelor’s Must have skills :AI/ Cloud, Test Design, Test Execution, Debugging and Triaging Skills, Communication Skills, Client Management Skills, Automation Skills What candidate will Be Doing: What we are looking for: Note – AI LLMs, Azure DevOps, Knowledge on C#, Test Automation *******************************************************************************************************************************************

Position: MCAD Engineer (CE57SF RM 3510) Shift timing : 9 to 6 pmRelevant Experience required: Min 5 years of industry experience in product design, development, and manufacturing with technical background in mechanical assemblies that are related to motion control and structures.Education : Bachelor of Science in Mechanical Engineering (or equivalent experience) Must have skills:NX CAD, …

Position: Physical Design Engineer (IS100FF RM 3490) Responsibilities & Required Experience: *******************************************************************************************************************************************

Position: Design Verification Engineer (IS90FF RM 3489) Responsibilities & Required Experience: *******************************************************************************************************************************************

Position: Synthesis + STA Engineer (SI80FF RM 3488) Responsibilities & Required Experience: *******************************************************************************************************************************************

Position: TB, Env, Flow owner for DV (IS50FF RM 3486) Job Description:Familiar with TB architecture, define and implement DV flowsDV regression, Failure debugCoverage analysis, Coverage improvementsFamiliar with Cadence simulation toolsCoverage merger between simulation, formal and emulation· Lead : 5+ years exp. *******************************************************************************************************************************************

Position: GLS DV (SI50FF RM 3485) Job Description:TB, flow development for GLS , Integrate with RTL DV envGLS database creationUnit delay GLS, Power aware GLS, SDF timing based GLS at subsystem and SOC level· Lead : 5+ years exp. *******************************************************************************************************************************************