Analog Design Engineers (BB58FI RM 3938)

Position: Analog Design Engineers (BB58FI RM 3938)

Role Overview
We are seeking experienced Analog Design Engineers (Layout) with strong expertise in lower‑node semiconductor technologies, advanced layout design skills, and the ability to independently deliver high‑quality physical verification outputs.

Key Responsibilities

• Perform analog layout design for amplifier blocks, comparators, oscillators, ADCs, bandgaps, high‑speed circuits, SRAM, and power/capacitance circuits.
• Execute layout documentation and ensure high‑quality deliverables.
• Deliver clean and verified DRC/LVS databases.
• Work independently on lower‑node layout tasks with minimal supervision.
• Collaborate with circuit and verification teams during design cycles.
   
  Required Experience & Skills
• Semiconductor Node Expertise
  Mandatory hands‑on experience in:
  a) TSMC N12 and N16
  b) 12nm, 16nm nodes
• Strong exposure to:
  a)120nm, 130nm, 180nm nodes
• Foundry background:
  a) TSMC preferred
  b) Samsung/Intel experience acceptable
   
  Technical Skills
• Proficiency in layout design tools:
  a) Cadence Virtuoso
  b) GXL / MXL
  c) Synopsys layout tools (if applicable)
• Strong understanding of:
  a) Physical verification
  b) Layout methodologies
  c) Analog circuit fundamentals
• Ability to deliver high‑quality layout with minimal iterations.
   
  Nice-to-Have
• Synopsys StarRC
• R3D extraction experience

Experience Requirements

• Preferred: 5–8 years of analog layout experience
• Minimum: 3 years (only for exceptionally strong profiles)

Candidates must be capable of independently handling complete layout blocks without extensive training

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