Analog Layout Design Engineer (SI510FF RM 3682)

Position: Analog Layout Design Engineer (SI510FF RM 3682)

Required Qualifications:

• 5 to 10 years of experience in analog layout design.
• Proven experience in advanced nodes (7nm, 5nm, or below) is a must.
• Proficiency in layout tools such as Cadence Virtuoso, ICV, Calibre, Assura, etc.
• Strong understanding of analog layout constraints and techniques for high-performance and low-noise designs.

Preferred Skills:

• Experience in high-speed IO layout (e.g., SerDes, DDR, PCIe).
• Exposure to MBCFET and FinFET layout challenges and solutions.
• Understanding of ESD and latch-up prevention techniques.

*******************************************************************************************************************************************