IO Layout Engineers (SI48FT RM 3744)

Position: IO Layout Engineers (SI48FT RM 3744)

Qualification/Requirements

• Bachelors/master’s degree in Electronics & Communication/Electrical engineering.
• Working experience (4 to 8 years) in IO layout.
• Hands-on experience in layout design of IO blocks such as GPIO, Analog IOs , High Speed IOs and Pad ring.
• Experience in high-speed, low-power mixed-signal IP’s is a plus.
• Experience in TSMC 5nm layout (or below) using Virtuoso EXL features.
• Must have expertise on Totem EMIR & Self-heating effects, Star RC extraction, and Calibre PV checks (DRC, LVS, Antenna, ERC, PERC etc.).
• Good Understanding of layout fundamentals (Matching, EM, ESD, Latch up, coupling, crosstalk etc.).
• Experience in top-level floorplan, hierarchical layout methodologies.
• Good Verbal and written communication skills.
• Candidates having only memory/Standard Cell layout experience are not relevant to this requirement.

Role and Responsibilities:

• Will work on IO layout for ASIC controllers under guidance of senior team members.
• Collaborate closely with designers to understand the design constraints and create quality layout in efficient manner.
• Manage all the Sign Off PV & quality checks on an IP layout.

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