Power VCD Simulation Engineer (CE580SI RM 4587)

Position: Power VCD Simulation Engineer (CE580SI RM 4587)

Functional Area: GLS, Timing Closure, Power VCD simulation

Shift timing : 9-6
Work Mode : Work from office
Education Required: BE or ME Electronics

Experience Level:

• 1 Lead HC with 8+ years
• 3 Engineers HC with 5-8 years

Relevant Experience required:

• 1 Lead HC with 8+ years
• 3 Engineers HC with 5-8 years

Must have Skills:

• Lead and manage a team of 4 engineers responsible for Gate-Level Simulation (GLS) activities across 1-2 projects.
• Own and drive overall functional GLS execution, timing validation and timing closure support, including setup, debug, triage, and signoff readiness.
• Generate and validate power VCDs/SAIFs for power analysis and collaborate with implementation teams on power optimization.
• Ensure timely execution, status reporting, risk identification, and escalation to meet project milestones and deliverables.
• Closely align with Design, Physical Design (PD), DFT, and Verification teams to resolve issues and drive closure.
• Develop GLS methodologies, automation, and best practices to improve quality, efficiency, and turnaround time.
• Support silicon readiness by identifying late-stage functional, timing, reset, clocking, and power-related issues before tapeout.
• Drive task prioritization, and execution tracking to ensure predictable delivery against project schedules.
• Gate-level simulation, timing validation/closure, power activity (VCD/SAIF) generation, debug, and signoff readiness, with solid understanding of Design, PD, DFT, and STA flows.
• Proficiency in SystemVerilog/UVM, scripting (Python/Tcl/Perl/Shell), debug tools, and methodology development to improve quality and execution efficiency.
• Technical leadership, cross-functional collaboration, project planning, risk management, stakeholder communication, and driving teams to meet tapeout commitments and project milestones

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