Position: Design Verification Engineer (SystemVerilog/UVM) (BB50FT RM 4458) Job Description Job Qualifications Skills Required: ****************************************************************************************************************

Position: Mixed-Signal Co-Simulation Engineer (BB46FT RM 4457) Key Responsibilities Required Skills and Qualifications ********************************************************************************************************************************

Position: Semiconductor Design Engineer 2 (BB35FT RM 4456) Minimum Qualification Required: B.E./B.Tech in Electronics, M.Tech MSP Input – Supplier Inputs ***********************************************************************************************************************

Position: Jr. MSP Input – Supplier Inputs (BB35FT RM 4455) Minimum Qualification Required: B.E./B.Tech in Electronics, M.Tech Job Description: *********************************************************************************************************************

Position: Sr. MSP Input – Supplier Inputs (BB58FT RM 4454) Minimum Qualification Required: B.E./B.Tech in Electronics, M.Tech Candidate Skill: Digital & Analog Circuits Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Strong understanding of digital, analog and CMOS circuit concepts. Candidate Skill: SystemVerilog & UVM Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: …

Position: Mixed-Signal Verification Engineer (BB60FT RM 4426) Key skills: Mixed-Signal Co-Simulation, SystemVerilog, UVM, Verilog-AMS/RNM, Cadence Xcelium, Virtuoso, Spectre, Behavioral Modeling, Python/Perl/TCL, Model vs Schematic Verification **********************************************************************************************

Position: ASIC Engineer 2 (BB46FT RM 4425) Key Skills: ATPG Pattern Generation & Validation, Scan Insertion, DFT RTL/Gate-Level Implementation, Siemens/Synopsys/Cadence Tools, Verilog, VHDL, C/C++, TCL, Perl, Python. ********************************************************************************************************

Position: ASIC Engineer 4 (BB60FT RM 4424) Key Skills: SoC/IP Verification, SystemVerilog, UVM, PCIe, DDR, Test Controller, MBIST, DFT Architecture, AI Tools & Methodologies, Python/Perl/TCL. **********************************************************************************************

Position: Analog and Mixed Signal – Design Engineer – Analog – II (BB36FT RM 4423) Job Description: **********************************************************************************************

Position: Senior IP/SOC Design Engineer (BB810FT RM 4422) Responsibilities Job Description: Collaborate with cross-functional teams to ensure high-quality design implementation and successful product delivery. Required Skills and Qualifications *******************************************************************************************************