Position: AMS IP Verification (BB612FT RM 4437) Job Responsibilities: ********************************************************************************************************************

Position: HSIO PHY Verification (BB612FT RM 4436) Job Responsibilities: *********************************************************************************************************************

Position: FUNC PERF Cores Verification (BB612FT RM 4435) JOB RESPONSIBILITIES: REQUIREMENTS: *******************************************************************************************************************

Position: Java fullstack (TV60ST RM 4434) Mandatory skills: Java MSB , React\Angular, Vulnerability RemediationDomain: Banking domain Role SummaryWe are looking for a Senior Java Full Stack Engineer with strong experience in Java/MSB, React or Angular, and application vulnerability remediation. The candidate should have hands-on coding experience and be capable of analyzing and fixing security vulnerabilities …

Position: Java MSB + Bigdata (TV60ST RM 4433) Mandatory skills: Java MSB, any bigdata tool like Scala, Apache Spark, SQOOP, Vulnerability RemediationDomain: Banking domain Role SummaryWe are looking for a senior Java professional with 6+ years of experience in Java development, Big Data technologies, and application vulnerability remediation. The candidate should have strong hands-on coding …

Position: Java MSB (Microservices, Springboot) (TV60ST RM 4432) Mandatory skills: Java MSB, SQL, AWS + Vulnerability remediationDomain: Banking domain Role SummarySenior engineer to handle the more complex, code-intensive remediation flagged by SVA (static), DVA (dynamic), SCA, and container scans across the Java portfolio. Key Responsibilities Mandatory Skills ************************************************************************************************************************

Position: Design Verification Engineer (BB810FF RM 4431) ABOUT THE ROLEWe are looking for an experienced Design Verification Engineer to join a high-speed networking ASIC programme on a contract basis. You will work as part of a team verifying complex IP blocks and subsystems, contributing independently from day one. The role requires strong hands-on UVM and …

Position: Mixed-Signal Verification Engineer (BB60FT RM 4426) Key skills: Mixed-Signal Co-Simulation, SystemVerilog, UVM, Verilog-AMS/RNM, Cadence Xcelium, Virtuoso, Spectre, Behavioral Modeling, Python/Perl/TCL, Model vs Schematic Verification **********************************************************************************************

Position: ASIC Engineer 4 (BB60FT RM 4424) Key Skills: SoC/IP Verification, SystemVerilog, UVM, PCIe, DDR, Test Controller, MBIST, DFT Architecture, AI Tools & Methodologies, Python/Perl/TCL. **********************************************************************************************

Position: Analog and Mixed Signal – Design Engineer – Analog – II (BB36FT RM 4423) Job Description: **********************************************************************************************