Position: Security Operations Lead (CE100ST RM 4554) Security Operations Lead: Your expertise: **********************************************************************************************************************

Position: Simulation Acceleration Engineer (BB810FT RM 4553) Key skills: Palladium or Zebu simulation acceleration, acceleration methodology, RTL/TB profiling for speed improvement, accelerated VIPs, large dump debugging, SystemVerilog/UVM, VCS/Xcelium, and Verdi/Verisium. Preferred exposure: AXI, AHB, APB, CHI, PCIe Gen6+, USB3+, Gigabit Ethernet, UCIe, memory standards, Python, and AI-enabled regression/debug flows. Required Qualification Technical Skills Soft Skills …

Position: Secure development & assurance lead (CE100SF RM 4552) Secure Development and Assurance Lead: Your expertise: *********************************************************************************************************************

Position: Security Architecture Lead (CE100ST RM 4550) Security Architecture Lead: Your expertise: ********************************************************************************************************************

Position: RTL Integration Engineer – PCIe Gen5 to Gen8 (BB812FI RM 4549) Key skills: PCIe Gen5+ controller and PHY integration, PCIe protocol layers (TL/DL/PHY), LTSSM, TLP/DLLP, flow control, replay, PIPE interface, multi-clock design, CDC, reset sequencing, and AXI/APB-based SoC integration. Must have silicon-proven PCIe Gen5+ experience; exposure to PCIe Gen6 FLIT-mode architecture is strongly preferred. …

Position: Senior Physical Design Engineer (3nm) (BB812FI RM 4548) Key skills: Block-level PnR from floorplan to GDSII, multi-GHz timing closure, CTS, OCV/POCV, SI, IR/EM, DRC/LVS, ECO, and metal-fill. Tools required: Synopsys Fusion Compiler/ICC2 or Cadence Innovus, PrimeTime, StarRC/Quantus, Calibre, RedHawk/Voltus, TCL, and Python. Must have hands-on 3nm (TSMC N3E/N3P or equivalent) full-block implementation through tape-out; …

Position: Design Verification Engineer – High-Speed Networking ASIC (BB810FI RM 4547) Key skills: SystemVerilog, UVM, SVA, coverage-driven verification, regression management, Synopsys VCS, and Verdi.Preferred exposure: Ethernet, MACsec, IPSec, PCIe, high-speed serial interfaces, or switching ASIC verification. ABOUT THE ROLEWe are looking for an experienced Design Verification Engineer to join a high-speed networking ASIC programme on …

Position: ASIC/FPGA Design & Verification (BB58FI RM 4546) Job Description: ***************************************************************************************************************************

Position: Research & Development – RF, Analog and Mixed Signal – Design Engineer – Analog – III (RM 4539) Domain – Analog FE. Experience – More than 12 years. Scope of Responsibilities: AsiaPac “Design Enablement Engineering Support” team is focused on the implementation of methodology in close collaboration with the AsiaPac design teams and on …

Position: Senior Software Engineer (CE50SF RM 4542) Role Summary:We are looking for an experienced Senior Software Engineer to join our Avionics team. The ideal candidate will have strong avionics software development experience, mandatory hands-on experience in Flight Management Systems, and expertise in developing safety-critical software in a DevOps environment. The role requires ownership of product …