Position: Observability & FinOps (TT70ST RM 4347) Interview process – Virtual interview Must have skills: ****************************************************************************************************

Position: RUCA (TT70ST RM 4346) Interview process – Virtual interview Must have skills: *****************************************************************************************************

Position: GitHub Enablement (TT70ST RM 4345) Interview process – Virtual interview Must have skills: **************************************************************************************************

Position: SW Enterprise Data & BI (TT70ST RM 4344) Interview process – Virtual interview Must have skills: ********************************************************************************************************

Position: DevX (TT70ST RM 4343) Interview process – Virtual interview Must have skills: *************************************************************************************************************

Position: Senior Formal Verification Engineer (BB80FT RM 4341) Role OverviewWe are looking for a Senior Formal Verification Engineer to own formal sign-off for complex, highspeed IP blocks and subsystems. The ideal candidate combines deep formal methodology expertise with strong hands-on SystemVerilog/UVM verification experience on complex protocol IPs such asDDR, PCIe, and Ethernet. Key Responsibilities● Own …

Position: Classic AUTOSAR Communication (COM) Experts (TK613SI RM 4334) Work mode: 5 DAYS WORK FROM OFFICE MANDATORY SKILLS : Classic AUTOSAR Architecture, Communication Stack, Network Protocols, Programming and Debugging,V ector DaVinci Configurator, DaVinci Developer, CANoe, CANalyzer, and Git/GitLab.,ASPICE work-product understanding for SWE.1 to SWE.6, reviews, traceability, and release discipline. PREFERRED SKILLS : MCAL, RTE, BSW,CAN, …

Position: AMS Spice Verification Consultant (BB510FT RM 4333) Job Description: ****************************************************************************************************************

Position: ASIC STA Engineer (BB60FT RM 4332) Role : Looking for an experienced ASIC STA Engineer with strong hands-on expertise in pre/post-layout STA and timing closure. Key Responsibilities Must Have ******************************************************************************************************************

Position: Senior DV Engineer – UVM/SystemVerilog (BB810ST RM 4328) Very good knowledge of UVM and SystemVerilog.Some networking experience/exposure is welcome. *************************************************************************************