Position: AMS (BB80FT RM 4514) Job Description:You are responsible for the delivery of a fully verified physical design, which meets all technical requirements, both at IP level and toplevel. The standard flow exists of floorplanning, placement, (toplevel) routing, verification and design finishing. This is done in a Cadence design environment combined with appropriate tool and …

Position: FPGA Opening (BB120FT RM 4513) Preferred Qualifications Technical Skills Emulation Platform Experience Soft Skills ************************************************************************************************************************

Position: Camera Device driver and PCIe driver development (TK1013BT RM 4512) MANDATORY SKILLS : Camera driver, low-level PCIe driver protocols, QNX, GMSL2, I2C, and DSI protocols, C/C++, PCIe driverPREFERRED SKILLS : Qualcomm 8650P and QNX 8.0., unit testing Job Description: ***********************************************************************************************************

Position: Java MSB + AWS + React (TV60CT RM 4501) Domain : Banking domain Skills required : Java MSB + AWS + React ****************************************************************************************************************

Position: Java MSB + AWS + Kafka, Multithreading (TV60CT RM 4500) Domain : Domain : Banking domain Skills required : Java MSB + AWS + Kafka, Multithreading ****************************************************************************************************************************

Position: Java MSB + AWS + Vulnerability Remidiation (TV60CT RM 4499) Domain : Banking Mandatory skills: Skills required : Java MSB + AWS + Vulnerability Remidiation ********************************************************************************************************************

Position: Java MSB + AWS + Vulnerability + Agentic AI (TV60CT RM 4498) Mandatory skills: Skills required : Java MSB + AWS + Vulnerability + Agentic AI ********************************************************************************************************************

Position: Senior Verification Engineer, DDR PHY (IRT60ST RM 4494) Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY. Must-have: Good to have: ****************************************************************************************************************

Position: Senior Verification Engineer, High-Speed IO (SoC) (IRT60ST RM 4493) SoC-level verification of high-speed interface IP, including test porting, regression and silicon bring-up support. Skills Looking for: ****************************************************************************************************************************

Position: Middleware Systems Engineer (CE40SF RM 4492) Required Nice to Have *********************************************************************************************************************